Verilog

HDLBits HDLBits 是一系列小型電路設計的練習，用於使用 Verilog 硬體描述語言(HDL)進行數位硬體設計。 由教學的題型由淺入深，逐步建立起電路設計的技能。 每個問題都會要求讀者使用 Verilog 設計一個小電路。HDLBits 會對提交的程式碼作判讀。透過一組測試碼來進行向量模擬，並與解答比較，檢查正確性。 Catalog 1. Getting Started 2. Verilog Language 3. Circuits 4. Verification: Reading Simulations 5. Verification: Writing Testbenches 6. CS450 1 Getting Started \(\text{assign one}\) Build a circuit with no inputs and one output. The output should always drive 1 (or logic high). module top_module( output one); assign one = 1'b1; endmodule \(\text{assign zero}\) Build a circuit with no inputs and one output that outputs a constant 0....

1. Getting Started 2. Verilog Language 3. Circuits 4. Verification: Reading Simulations 5. Verification: Writing Testbenches 6. CS450 2 Verilog Language 2.1 Basics wire Create a module with one input and ont output that behaves like a wire module top_module( input in, output out); assign out = in; endmodule multi-in-out Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections: module top_module( input a,b,c, output w,x,y,z ); assign w = a; assign x = b; assign y = b; assign z = c; endmodule not gate Create a module that implements a NOT gate....

1. Getting Started 2. Verilog Language 3. Circuits 4. Verification: Reading Simulations 5. Verification: Writing Testbenches 6. CS450 3 Circuits 3.1 Combinational Logic 3.1.1 Basic Gates Wire module top_module ( input in, output out); assign out = in; endmodule GND module top_module ( output out); assign out = 1'b0; endmodule NOR module top_module ( input in1, input in2, output out); assign out = ~(in1|in2); endmodule Another Gate module top_module ( input in1, input in2, output out); assign out = in1 & (~in2); endmodule Two gates module top_module ( input in1, input in2, input in3, output out); wire w1; assign w1 = ~(in1^in2); assign out = w1^in3; endmodule More logic gates module top_module( input a, b, output out_and, output out_or, output out_xor, output out_nand, output out_nor, output out_xnor, output out_anotb ); assign out_and = a & b; assign out_or = a | b; assign out_xor = a ^ b; assign out_nand = ~(a & b); assign out_nor = ~(a | b); assign out_xnor = ~(a ^ b); assign out_anotb = a & (~b); // and(out_and, a, b); // or(out_or, a, b); // xor(out_xor, a, b); // nand(out_nand, a, b); // nor(out_nor, a, b); // xnor(out_xnor, a, b); // and(out_anotb, a , ~b); endmodule 7420 chip module top_module ( input p1a, p1b, p1c, p1d, output p1y, input p2a, p2b, p2c, p2d, output p2y ); assign p1y = ~(p1a & p1b & p1c & p1d); assign p2y = ~(p2a & p2b & p2c & p2d); endmodule\ Truth tables \(\begin{array}{|c|ccc|c|}\hline \text{Row}&&\text{Inputs}&&\text{Outputs}\\\hline \text{number}&\text{x3}&\text{x2}&\text{x1}&\text{f}\\\hline 0&0&0&0&0\\\hline 1&0&0&1&0\\\hline 2&0&1&0&1\\\hline 3&0&1&1&1\\\hline 4&1&0&0&0\\\hline 5&1&0&1&1\\\hline 6&1&1&0&0\\\hline 7&1&1&1&1\\\hline \end{array module top_module( input x3, input x2, input x1, output f ); assign f = ((~x3)&x2)|(x3&x1); endmodule Two-bit equality Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and produces an output z....

4 Verification - Reading Simulations 4.1 Finding bugs in code 4.2 Build a circuit from a simulation waveform 1. Getting Started 2. Verilog Language 3. Circuits 4. Verification: Reading Simulations 5. Verification: Writing Testbenches 6. CS450

5 Verification - Writing Testbenches 1. Getting Started 2. Verilog Language 3. Circuits 4. Verification: Reading Simulations 5. Verification: Writing Testbenches 6. CS450